This invention relates to the stacking of layers containing IC chips, therby obtaining high density electronic circuitry. In general, the goal of the present invention is to combine high circuit density with reasonable cost. Cost reduction involves (a) relatively low cost initial forming of layers, (b) ability to use simple layer-testing techniques, and (c) effective ways of guaranteeing that defective layers will not be included in the stacks.
Another aspect of successful stacking of chip-containing layers is the availability of large numbers of input/output (I/O) terminals (or pads) for connecting the stack to external circuitry.
In most of the extensive prior art disclosures, the leads from the chip-embedded IC circuitry are brought out at one or more sides of the stack, i.e., at the periphery of the stacked layers. Some packages bring conductors from the IC circuitry through vertical vias extending to the bottom of the package, permitting the use of I/O pads on the bottom of the package, i.e., ball grid arrays of terminals on a single flat surface.
Hayden et al U.S. Pat. No. 5,579,207 shows a structure in which stacked chip-enclosing layers have vertically-extending vias serving as conductors between the IC chips and a plurality of pads on the top and bottom of the stack. Each layer substrate (chip carrier) in the Hayden et al patent has an IC chip mounted on its upper surface, and a cavity formed in its lower surface, which provides space for the IC chip on the layer below. The layers are separately formed and then stacked, using flat sealing strips around the peripheral edge between adjacent layers to provide sealing of the cavities, i.e., sealing occurs as a result of stacking. Because the Hayden et al patent extends the IC chip mounted on one carrier into the cavity of the next carrier, it is not possible to pretest the individual carriers as sealed, or covered, units.
What is not available in the prior art is a stack of IC-chip-containing layers which can be fully tested individually prior to stacking, and can connect the chip circuitry through vias to a ball grid array at the bottom of the stack, which array may if desired have terminals located at points throughout the full planar surface.